下周6月20日开始 Xilinx与北京工业大学共建的4门本科嵌入式方向双语课程之中的2门课程, 这里简要介绍一下情况:
第一门课,
DSP Design Technology using FPGAs
采用FPGA的数字信号处理技术
讲课教授是大家都很熟悉的苏格兰的Bob Stewart教授. 原先他来中国讲授了不少2天的Workshop, 反响很好, 这次,在2天的Workshop的基础上, 针对本科生的情况,并结合目前3G, OFDM, LTE, MIMO等热门技术. 这次他带来两名助教,也都是来自苏格兰. 整个课程30%都是基于XILINX的大学计划板XUPV5的实验.
第二门课,
Software/Hardware Co-Design with BEEcube Platform Studio
采用BEECUBE BPS的软硬件协同设计
这门课程的课件, 是加州大学伯克利分校的John Wawrzynek教授今年刚刚开发完成的新课CS150, 刚刚在UC Berkley上了一遍,就由他以前的学生,创办Beecube公司的CEO, Chen Chang (章晨) 博士, 不远万里,带到中国来教授此课. 最后的课程设计将会有竞赛, 赢家会获ipod奖励.
两门课程均面向北京工业大学软件学院嵌入式方向培养模式创新实验区的本科3年级学生讲授, 同时欢迎感兴趣的老师和工程师旁听. 报名请联系依元素公司, 或者直接联系北京工业大学的严海荣老师.
附上教学大纲,供参考:
DSP Design Technology using FPGAs
BJUT, June 2011
Type: Professional Course
Period: 30
Credit Hour: 3
Teaching Materials: Xilinx DSP Primer
Lecturer: Prof Bob Stewart, University of Strathclyde, Scotland, UK
Assistant Lecturer: Dr Louise Crockett, University of Strathclyde, Scotland, UK
Lab Assistant: Mr Tony Gao, University of Strathclyde, Glasgow, Scotland, UK
In recent years, the growth of wireless and wireline digital communication has increased exponentially, driven both by the continued growth in consumers and the uptake of bandwidth-hungry explosive applications, such as YouTube, Google, and online on-demand TV services. In the last 10 years the migration from low-speed dial-up modem connections of a few kbit/s to DSL broadband speeds of Mbits/s changed the way everybody uses a computer. Up next is another migration, perhaps taking fixed point wireless connectivity of a few MBits/s using 802.1x standards to the true anytime, anywhere, anyplace mobile wireless connectivity likely to be offered by new technologies such as 3G-LTE. Add to this the continued demand for very high-speed radar, defense systems, and space-based communications and there is one common element: very high-speed digital signal processing requirements. And best placed to offer flexibility, reprogramability, and incredible levels of processing power is the FPGA.
In this intensive short course, the use of FPGAs is looked at specifically for DSP algorithms, applications, and architectures. Particular emphasis is on communications given the widespread use of FPGAs in this market and the sheer variety of problems to be solved. The course features both simulation and real design onto FPGA DSP boards provided in the laboratory session of the course.
Instruction covers:
· When to use an FPGA rather than a DSP processor or core
· The current "processing" power offered by FPGAs and different vendors
· How to efficiently implement DSP algorithms on FPGAs
· The issues and new design paradigms concerning wordlength and high sampling rates
· The different ways to structure the arithmetic required for DSP
· The issues of numerical rounding and truncation, saturation and wraparound, overflow and underflow
· Techniques to simplify the arithmetic (oversampling, CIC filters, etc.)
· How to partition and design a DSP algorithm to run efficiently on an FPGA
· Working with feedback DSP algorithms and architectures
· How to implement advanced communication systems on FPGAs
· The strategy of using FPGA and DSP design software
· Design, simulate, and FPGA implementations of adaptive systems
· Design of Direct Digital Downconverters (DDC) and Direct Digital Upconverters (DUC)
· Adaptive DSP architectures based on the QR Algorithm (beamforming, beamsteering MIMO)
· Working with embedded processors on FPGAs
· Digital communications numerical oscillators, and carrier and symbol synchronization on FPGAs
The course is presented in the following format:
· Approximately 60 percent lectures and FPGA-DSP demonstration
· Approximately 30 percent hands-on laboratory on FPGA-DSP design/simulation and real hardware design using the Xilinx devices
· 10 percent responsive mode to questions, concerns, and requests
Laboratory Sessions
Participants work with industry-standard FPGA design tools and learn the complete design flow, from DSP bit-true design and simulation design to producing VHDL for synthesis to actual FPGA implementation. Xilinx Virtex v5 FPGAs are targeted and all participants take their implementation onto real devices.
Syllabus
1. Introduction to DSP Hardware Technologies
· From discrete logic to FPGAs
· The generic DSP system
· DSP cores and processors review
· Custom and semi-custom ASICs
· System-on-chip (SOC)
· FPGA flexibility and functionality
· FPGAs vs. programmable DSPs
· How fast is fast?
2. Linear Systems DSP Algorithm Review
· Aliasing and reconstruction filters
· Sampling rates and wordlengths
· Z-domain notation and fundamental analysis
· Frequency domain analysis
· Finite Impulse Response (FIR) digital filters
· Infinite Impulse Response (IIR) digital filters
· Digital filter design and specification techniques
· Oversampling techniques and Sigma Delta
3. FPGA Technology
· The FPGA technology roadmap
· Clocking rates, data rates, and sample rates
· FPGA memory and registers
· Input/output blocks and requirements
· Programmable interconnects
· FPGA vendors/manufacturers
· Bits, slices, and configurable logic blocks
· Comparable MIPs performance ratings
· FPGA families and sources
· Some comment on need-to-know VHDL
4. DSP Arithmetic Fundamentals
· 2's complement fixed-point arithmetic
· Fundamental adders and multiplier arrays
· Division and square root arrays...not so easy
· Wordlength issues
· Fixed-point arithmetic
· Overflow and underflow
· CORDIC techniques for trigonometric calculations
· Complex arithmetic requirements
5. FPGA Elements for DSP Algorithms
· Building delay lines and shift registers
· Use of RAM (memory) on FPGAs
· Serial to parallel and parallel to serial
· Multiplexors for channel selection
· Full adders, carry logic, and adder trees
· Multipliers: shift and add; ROM-based
· (K)Constant Coefficient Multiplier (KCM)
· Minimum size multipliers
· Dedicated on-chip "hardware" multipliers
6. Signal Flow Graph (SFG) Techniques
· DSP/digital filter signal flow graphs
· Latency, delays, and "anti-delays"
· Re-timing: cut-set techniques
· Delay scaling and multichannel implementations
· The transpose FIR
· Pipelining and multichannel architectures
· Old ideas—new enthusiasm: systolic arrays
· SFG topologies for FPGAs
7. "Strategic" Digital Filtering for FPGAs
· Symmetric/linear phase filters
· Upsampling and interpolation filters
· Downsampling and decimation filters
· 1-bit oversampled (sigma-delta) data streams
· Efficient arithmetic for FIR implementation
· Integrators and differentiators
· Half-band, moving average, and comb filters
· Cascade Integrator Comb (CIC) Filters (Hogenauer)
· Efficient arithmetic for IIR filtering
8. Adaptive DSP Algorithms and Applications
· LMS algorithms
· FPGA pipelining techniques
· Non-canonical LMS algorithms for FPGA
· The QR Algorithm for matrix "inversion"
· Givens rotations for QR implementation
· The QR triangular array
9. DSP-Enabled Communications Using FPGAs
· Quatenary Phase Shift Keying (QPSK) and variants
· Transmit/receive filters—root-raised cosine
· Undersampling and direct digital downconversion
· Direct digital upconversion
· Digital IF stages (and fs/4 systems)
· Spread spectrum
· Design partitioning for Xilinx FPGA
10. Case Studies Design, Simulation, and Implementation
· Design of optimized 3G transmit root raised cosine filters
· Adaptive QR equalizer at fs = 10MHz
· Numerically controlled oscillator design
· High-speed FFT implementation
· High-speed CIC filter design
· 80MHz IF Direct Digital Downconverter (DDC)
· Complex multiplier phase rotator
· Timing and synchronization circuits
· Spread spectrum: chipping and channelization implementation
11. Course Mini Project Topic
· Design of audio DSP communication system
Software/Hardware Co-Design with BEEcube Platform Studio
By Chen Chang, PhD CEO of BEEcube
Course Overview
This course uses the state-‐of-‐art SW/HW co-‐design methodology from BEEcube to introduce the students to the latest embedded system design techniques. The focus is
hands-‐on skills to design from algorithm to full SW/HW implementation targeting FPGA.
During the 5-‐day long course, students will be attending lectures in the morning and lab
project design in the afternoon. The course lab project material is designed by professor
John Wawrzynek at University of California Berkeley for CS150 class in Spring 2011. Students
will be implementing a full video graphics accelerator on Xilinx XUPV5 FPGA platform. At
the end of the course, a design competition will be held and the best design winner will be
awarded the latest Apple iPod.
KeySkills
• Embedded system design from algorithm to software implementation
• Hardware acceleration of software implementation
• Software/hardware interface design
• Video graphics rendering techniques
• DRAM interface and video frame buffer design
• System integration and optimization
• CAD tool usage including Xilinx ISE/EDK/SysGen, BEEcube Platform Studio,MathWorks
Matlab and Simulink Course Schedule
